Default NaN Mode

When bit 25 in the FPSCR is set, default NaN mode is enabled. When this mode is enabled, any operation which generates a NaN, or takes a NaN as an input will return the default NaN as the result. Note that enabling this is not IEEE compliant.

Enabling Default NaN Mode:

VMRS r0, FPSCR
ORR r0, r0, #(1 << 25)
VMSR FPSCR, r0

Disabling Default NaN Mode:

VMRS r0, FPSCR
BIC r0, r0, #(1 << 25)
VMSR FPSCR, r0

Notes

• On the VFPv2 coprocessor, the sign bit of the default NaN is considered UNKNOWN.
  • However, within the VFPv2 implementation used in the 3DS, the sign bit of the default NaN is always positive.
    • Single-precision default NaN: 0x7fc00000
    • Double-precision default NaN: 0x7fc0000000000000