The APSR, CPSR, SPSR, and the Difference Between Them
APSR – Application Program Status Register
- Only holds copies of the ALU status flags (AKA condition code flags).
- Flags here determine whether or not an instruction is executed, with two exceptions
- On ARMv6 and later, GE (Greater than or Equal) flags are present. These are used by the SEL instruction to perform byte selection.
- On ARMv5TE, ARMv6 or later, the Q flag is present. This is set by saturation instructions
The APSR on the ARM11 MPCore takes the form:
| 31 |
30 |
29 |
28 |
27 |
26 - 24 |
23 - 20 |
19 - 16 |
15 - 0 |
| N |
Z |
C |
V |
Q |
RAZ/SBZP |
Reserved/UNK/SBZP |
GE |
Reserved/UNK/SBZP |
CPSR – Current Program Status Register
- Contains:
- The APSR flags
- Current instruction set state
- Execution state bits for the Thumb If-Then (IT) instruction (RAZ in the 3DS ARM processors; not capable of executing IT).
- Current endianness (E bit, bit 9)
- Current processor mode (bits 0 - 4)
- Interrupt and asynchronous abort disable bits
The CPSR on the ARM11 MPCore takes the form:
| 31 |
30 |
29 |
28 |
27 |
26 - 25 |
24 |
23 - 20 |
19 - 16 |
15 - 10 |
9 |
8 |
7 |
6 |
5 |
4 - 0 |
| N |
Z |
C |
V |
Q |
RAZ |
J |
Reserved/UNK/SBZP |
GE |
RAZ |
E |
A |
I |
F |
T |
M[4:0] |
SPSR – Saved Program Status Register
- All processor modes except system and user mode have an SPSR.
- Records the pre-exception value of the CPSR.
- Upon taking an exception, the CPSR is copied to the SPSR of the processor mode the exception is taken to.
- This is useful because the exception handler is able to restore the CPSR to the value prior to taking the exception, as well as being able to examine the CPSR in general.