APSR and CPSR Flags
The CPSR (which contains the APSR):
| 31 |
30 |
29 |
28 |
27 |
26 - 25 |
24 |
23 - 20 |
19 - 16 |
15 - 10 |
9 |
8 |
7 |
6 |
5 |
4 - 0 |
| N |
Z |
C |
V |
Q |
RAZ |
J |
Reserved/UNK/SBZP |
GE |
RAZ |
E |
A |
I |
F |
T |
M[4:0] |
| Flag |
Description |
| N (Negative) |
Set if the result of a data processing instruction was negative |
| Z (Zero) |
Set if the result of an instruction operation is zero |
| C (Carry) |
Set if the result of an unsigned operation overflows the 32-bit result register |
| V (Overflow) |
Same as the carry flag, but for signed operations |
| Q (Saturation) |
Set if saturation occurs during execution of a saturation instruction. This flag is sticky; it must be explicitly cleared by an MSR instruction. |
| J (Jazelle) |
Set when the CPU is in Jazelle mode |
| GE (Greater than or Equal) |
Used by the SEL instruction for byte selection |
| E (Endian) |
Controls the endianness for load/store instructions. When cleared, load/store instructions operate in little-endian. When set, load/store instructions operate in big endian. |
| A (Abort) |
Controls whether or not imprecise data aborts are disabled. |
| I (IRQ) |
Controls whether or not IRQ interrupts are disabled. |
| F (FIQ) |
Controls whether or not FIQ interrupts are disabled. |
| T (Thumb) |
Indicates if the processor is in Thumb mode. If set, Thumb mode is active. If cleared, Thumb mode is not active. |
| M (Mode) |
Indicates the current processor mode. See table below |
This table shows what processor modes correspond to mode bit configurations.
| Bits |
Mode |
| 10000 |
User |
| 10001 |
FIQ |
| 10010 |
IRQ |
| 10011 |
Supervisor |
| 10111 |
Abort |
| 11011 |
Undefined |
| 11111 |
System |
Notes
- Despite the ARM11 MPCore in the 3DS having the Jazelle bit, the 3DS doesn't actually support Jazelle.
- However, it does support the instruction that attempts to enter Jazelle mode (BXJ). Attempts to use it will make it function like a BX instruction.