Nintendo 3DS ARM Documentation

FPSCR - Floating-Point Status and Control Register

  • Read/write register
  • Accessible in privileged and unprivileged modes.
  • Contains VFP status and control bits.

Layout:

31 30 29 28 27 - 26 25 24 23 - 22 21 - 20 19 18 - 16 15 14 - 13 12 11 10 9 8 7 6 - 5 4 3 2 1 0
N Z C V SBZ DN FZ Rmode Stride SBZ LEN IDE SBZ IXE UFE OFE DZE IOE IDC SBZ IXC UFC OFC DZC IOC

Bitfields:

Bit(s) Name Meaning
31 N Set if comparison produces a less than result
30 Z Set if comparison produces an equal result
29 C Set if comparison produces an equal, greater than or unordered result
28 V Set if comparison produces an unordered result
27:26 - Should Be Zero
25 DN Default NaN mode enable bit
24 FZ Flush-to-zero mode enable bit
23:22 Rmode Rounding mode control field. See table below for possible values
21:20 Stride Vector stride
19 - Should Be Zero
18:16 LEN Vector length
15 IDE Input Subnormal exception enable bit
14:13 - Should Be Zero
12 IXE Inexact exception enable bit
11 UFE Underflow exception enable bit
10 OFE Overflow exception enable bit
9 DZE Division by Zero exception enable bit
8 IOE Invalid Operation exception enable bit
7 IDC Input Subnormal cumulative flag
6:5 - Should Be Zero
4 IXC Inexact cumulative flag
3 UFC Underflow cumulative flag
2 OFC Overflow cumulative flag
1 DZC Division by Zero cumulative flag
0 IOC Invalid Operation cumulative flag

Rounding modes:

Bits Mode
b00 Round to nearest (RN) mode
b01 Round towards plus infinity (RP) mode
b10 Round towards minus infinity (RM) mode
b11 Round towards zero (RZ) mode