ARM processors have privilege modes which allow preventing certain operations by an executing process. The privilege modes the CPUs in the 3DS have are the following:
| Mode | Description |
|---|---|
| User | Unprivileged mode. Applications normally run in this mode |
| System | Runs applications with elevated privileges. System mode can be viewed as a cross between user and supervisor modes. It provides the privileges of supervisor mode, but shares registers with user mode. |
| FIQ | ARM processors have two types of interrupt types: regular interrupts, and fast interrupts (FIQs). The only difference between fast interrupts and normal interrupts is that fast interrupts can interrupt regular interrupts (kind of a mouthful to say). Since ARM processors do not have non-maskable interrupts (NMIs), FIQs can be disabled when necessary. Interrupts that need to complete very quickly will use this mode. |
| IRQ | Regular interrupt mode. Interrupts that are not time-critical (not requiring clock timing accuracy) will normally use this mode. |
| Supervisor | Privileged mode for the operating system. |
| Abort | This mode is entered whenever an abort exception occurs. |
| Undefined | This mode is entered whenever an undefined instruction exception is signalled. Normally whenever an undefined instruction exception is encountered, the ARM processor will wait and see if any coprocessors are able to handle the instruction. If not, then the undefined instruction vector is taken. Some software can actually utilize this form of exception handling to software emulate undefined coprocessor instructions |
On the ARM11 MPCore both cores run in user mode. In user mode, access to certain other registers is not possible (such as a majority of the registers in the CP15 coprocessor). It isn't possible to explicitly switch to a higher privileged mode from user mode.
Note that each mode can also have it's own registers that 'shadow' the original core 15 registers. These are known as banked registers. These registers are automatically brought into 'view' (possible to read/write to) whenever the processor changes into modes that have these registers.
Which registers are to be shadowed in a processor mode are different. The table below depicts the registers shadowed per mode in the ARM11 MPCore.
| Mode | Shadowed Registers |
|---|---|
| User | No shadowed registers |
| System | Shares registers with user mode |
| Supervisor | SP, LR, CPSR |
| Abort | SP, LR, CPSR |
| Undefined | SP, LR, CPSR |
| IRQ | SP, LR, CPSR |
| FIQ | R8, R9, R10, R11, R12, SP, LR, CPSR |